Samsung Breaks Cache Memory Price/Performance Barrier

"One Speed Fits All" Pipelined Burst SRAM Provides Lowest-Cost Way to Top Performance in Next-Generation Desktop and Portable PCs

SAN JOSE, Calif., April 4, 1994 -- Designers of next-generation PC memory systems caught between costly burst SRAMs and low-performance asynchronous SRAMs can now attain top performance at low cost with a revolutionary memory device announced today by Samsung Semiconductor, Inc. The synchronous pipelined burst SRAM enables desktop and portable PC makers to unleash the full power of their Pentium-, PowerPC and i486-based systems without paying a penalty for high performance.

A true 3.3-volt device, Samsung's synchronous pipelined burst SRAM employs a trend-setting "one speed fits all" design, meaning PC makers will be able to use the same chip at the same price to satisfy all their cache memory speed requirements, up to 75 MHz. And there is no price premium for speeds above 50 MHz. Initially available in a 32K by 32, 1-megabit density, even denser chips can be plugged in when available without system redesign because subsequent members of this product family will be packaged with identical pinouts and AC characteristics, providing PC makers with unparalleled flexibility.

"It's ridiculous for designers to continue to pay the outrageous premiums commanded by burst SRAMs for only marginally better performance than they can achieve with our pipelined alternative," said Robert Eminian, Samsung's assistant director of marketing. "With the high yields we can achieve, the synchronous pipelined burst SRAM is destined to be a commodity part, with commodity pricing, that will meet designers' performance needs now and well into the future."

One Speed, One Price

Until now, Pentium- and PowerPC-based computer makers had only two alternatives for cache memory designs: costly BiCMOS burst SRAMs capable of sustaining near-zero-wait-state performance only up to 66 MHz, or CMOS asynchronous SRAMs, which above 50 MHz would cost even more than burst SRAMs while providing more limited two- or three-wait-state performance.

"A cache built using Samsung's synchronous pipelined burst SRAM has the same low cost whether it's designed for 50 MHz or 75 MHz," said Eminian.

Samsung's pipelined burst SRAM, however, delivers virtually the same performance as the burst SRAM, and can deliver it reliably up to 75 MHz and beyond. In addition, Samsung's highly integrated, low-power solution with sleep mode makes it practical for the first time to produce notebook PCs with the full power of a desktop system.

Samsung took great effort to work with leading PC OEMs to define the acceptable price/performance objectives for their synchronous pipelined burst SRAM. As a result, it is receiving wide industry support from second sources in both Japan and the U.S., and through forthcoming PC chipsets from major suppliers, including Samsung's own PC chipsets.

Smaller Die + CMOS Process = Higher Yield = Lowest Cost

Samsung has been able to dramatically improve the yields of its synchronous pipelined burst SRAM compared to BiCMOS burst SRAMs, especially at frequencies above 50 MHz. First, by placing registers between the RAM array and the CPU data bus, the memory core can actually operate more slowly than if it had to drive the data bus directly. This, in turn enables the RAM array to be implemented with a less costly, lower power CMOS process. Finally, by omitting the unnecessary parity bits and using finer design rules the die size can be reduced considerably, reducing costs even more.

"We're committed to making the synchronous pipelined burst SRAM a commodity solution," said Eminian. "It's the only thing out there that can deliver the required performance with a price structure suitable for the PC market." (See comparative cache cost charts attached.)

Synchronizing Memory

The KM732V588 and KM732V592 are 1,048,576-bit synchronous static random-access memories with 2-stage data and address pipelining designed specifically for 3.3-volt Pentium and PowerPC cache memories, respectively. Organized as 32,768 words by 32 bits, they are completely synchronous. All data, address and control inputs are sampled and all outputs are valid at the positive-going system clock edge, simplifying designs and giving designers much better control over their memory subsystems. The internal data, address and control latches, on-chip burst address generator and high-output drive circuitry increase performance while reducing or eliminating the need for external "glue" logic. This simplifies the design process, saves power and reduces electrical noise because the system does not need to generate all the addresses. The self-timed write capability relieves the system of this chore while eliminating write-cycle wait states. It's asynchronous sleep mode power management provides the power savings required by notebook PCs and helps all PC makers meet the EPA's Energy Star Standard.

"We've taken the complexity out of high-performance cache system design by integrating the data, address and control latches, burst address counter and write control timing into the SRAM itself," said Eminian. "Our pipelined design eventually will enable us to offer the most cost-effective high-performance cache systems up to 100 MHz."

In today's high-performance systems, the modest (i.e., 60- to 70-nanosecond) access speeds of dynamic RAM limit overall system performance by making the CPU wait for the data stored there. Although too expensive for use in a system's main memory, a small amount of fast static RAM acting as a cache buffer between the CPU and main memory reduces the CPU's need to wait, cost-effectively boosting overall system performance.

Pricing and Availability

The 1-megabit KM732V588 and KM732V592 synchronous pipelined burst SRAMs will begin sampling later this summer, and will cost $22 each for 75-, 66-, 60-, or 50-MHz versions. There is no premium for the higher speed parts. Production is expected to begin in the first quarter of 1995.

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