Samsung Re-Invents the DRAM

Synchronous Design Promises Economical Zero-Wait-State Performance to 100 MHz

SAN JOSE, Calif., February 22, 1993 -- Samsung Semiconductor today broke the memory bottleneck limiting microprocessor performance by announcing the industry's first fully synchronous dynamic random-access memory. The innovative KM48SL2000 byte-wide synchronous DRAM enables designers of high-end personal computers, engineering workstations and other high-performance, microprocessor-based systems to achieve up to 100-MHz operation easily, reliably and cost-effectively.

Until now, improvements in DRAM speeds, combined with interleaved memory and cache system designs incorporating small amounts of fast static RAM have enabled manufacturers to escalate system performance while keeping costs down. But as processor speeds of 50 MHz and above become common, even these hybrid designs are proving too slow, and have become a significant limit on overall system performance.

Samsung's solution is a new type of DRAM -- the synchronous DRAM -- capable of reading and writing bursts of information at 100-MHz speeds while maintaining the simplicity of the traditional DRAM interface.

"Samsung's synchronous DRAM offers a four hundred percent performance improvement over traditional asynchronous fast page mode DRAMs, enabling designers to extract the maximum performance out of today's microprocessors," said Mark Ellsberry, Samsung's director of marketing for memory products. "Only Samsung's evolutionary design approach achieves these performance goals without forcing engineers to learn memory subsystem design all over again."

Synchronizing Memory

The byte-wide 48SL2000 is completely synchronous, with all inputs sampled and all outputs valid at the positive-going system clock edge, simplifying designs and giving designers much better control over their memory subsystems.

Unlike traditional asynchronous DRAMs, which require the system to generate every address accessed, Samsung's synchronous DRAM requires only the starting address and a burst length of 2, 4, 8 or 512 (one page) bits. Once the burst begins, valid data is placed on the bus every clock cycle. When the burst ends, the tri-state outputs are automatically placed back in a high-impedance mode.

At 100 MHz with a burst length of 8 bits, for example, data is valid every 10 nanoseconds, resulting in 8 bytes of data (64 bits) in 80 ns. This not only increases performance, but also simplifies memory management, saves power and reduces system noise because the system does not need to generate all the column addresses.

"We've taken the complexity out of high-performance memory system design by integrating it into the DRAM itself," said Ellsberry. "Our synchronous design provides true pipelined performance that can fill a cache with completely random data at 100 MHz."

Bursts can be programmed to increment in standard binary count or using the Intel interleave count for greatly simplified integration into x86-based systems. The programmable nature of the burst count allows a single memory system to communicate easily with both AT and MicroChannel buses without adding to system complexity. Other programmable features of the 48SL2000 enable it to communicate over two buses of differing speeds with equal ease, and the 48SL2000 eliminates the need for column pre-charge.

The 48SL2000's single-bank/single-level-RAS design enables a simpler, more cost-effective system architecture than dual-bank/pulsed-RAS designs. It allows engineers to accomplish a significant performance leap quickly and easily because they can transfer their existing design expertise. And it offers design flexibility by making it possible to develop inexpensive memory controllers capable of handling both fast page and synchronous DRAMs.

Samsung's initial synchronous DRAM is a 16-megabit device organized as 2,097,152 words by 8 bits, fabricated using Samsung's proprietary 0.5 micron double-metal CMOS process. The 48SL2000 utilizes a standard JEDEC 3.3-volt power source, is low-voltage TTL compatible and features a multiplexed address bus. It is available in two package styles: a 32-pin SOJ and TSOPII (1.2-mm pitch) for operation up to and including 66 MHz, and a 44-pin TSOPII (0.8-mm pitch) for operation to 100 MHz.

Applications

With 80486-class microprocessors becoming commonplace, Pentium-class processors on the horizon and increasing price pressures on RISC-based workstations, there will be an increasing need for simpler, less costly high-performance memory systems. Samsung's synchronous memory design enables designers of engineering workstations, high-performance personal computers and other systems to achieve just that.

Using synchronous DRAMs, engineering workstations can run their memory subsystems as much as 400 percent faster than with traditional asynchronous fast page DRAMs. Cache fills can be accomplished in one-fourth the time required today. Workstations using interleaved design can use synchronous DRAMs without any increase in complexity to the controllers or the system design, and can achieve uninterrupted data flow with no dead time on the bus at 100 MHz. Data can move between memory and hard disks, for example, in a continuous flow.

Network servers and other high-performance personal computers can contain memory systems operating at 100 MHz that interface with processors running at 50 or 66 MHz. Disk I/O could be almost completely isolated from CPU performance. The processors would operate without wait states, and data could flow between memory and hard disks at 100 MHz.

Some embedded RISC applications could be designed without a secondary cache, operating out of main memory without a performance penalty. Massively parallel systems could obtain the bandwidth they need while maintaining the small footprint required of each node. Communication between multiple processors of differing speeds, such as between CPUs and specialized image processors, can be accomplished without complex dual-clock systems.

Pricing and Availability

Samples of Samsung's 48SL2000 synchronous DRAM are available now. In production quantities, Samsung anticipates the synchronous DRAM will be available for approximately a 20 percent premium over comparably sized traditional asynchronous DRAMs. Samsung also believes this premium could eventually drop to 10 percent or less.

Samsung is currently negotiating with other companies to provide second sourcing of the 48SL2000. At this time, both IBM and OBI have expressed their interest in technology exchanges that would provide them with the capabilities to produce these components.

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